In modern electronic devices such as mobile phones, computers etc. there is a continuous strive for miniaturization and close-packing of components. In the continuous strive of making micro components more densely packed, problems are encountered in particular where wafer through structures (also referred to as vias) are provided in very close proximity to each other. In particular where the vias are made from a material that is different from the substrate material in which they are provided, e.g. metal and silicon in the vias and substrate respectively, different thermal expansion effects may lead to substrates being subject to cracking and breaking during manufacturing, or other reliability issues during use.
Also, when vias are provided closer and closer, the requirement for routing signals over the substrate surface and in between above the vias becomes increasingly important. Thick Cu routing with reduced line width (CD) for improved performance (low R and C and ability to withstand high power density) is problematic.
Furthermore, routing patterns provided on the substrate surface will inevitably exhibit some degree of topography since the conductive material must have a finite thickness, and such topography can cause problems e.g. in the process of bonding wafers together, or when stacking several RDLs on top of each other for even more dense packaging (crossing of wires from different vias possible).
Among other things it is desirable to be able to stack chips carrying various devices on top of each other, so called interposers. Also, it is desirable to be able to provide so called redistribution layers, also referred to as routing structures, for signals coming from integrated circuits having large numbers of I/O contacts. Such contacts can be as many as several thousand on a chip of a size of the order of 10 mm square. If the signals are to be routed through the substrate, the through-substrate connections (vias) would have to be equally closely spaced. When such vias are made of metal and very closely spaced, thermal expansion effects due to different coefficients of expansion may cause damage to the very thin and brittle chips in which they are made. This frequently occurs both during processing but also in use in the end product, if it is subjected to temperature changes over large intervals. Also, the thickness of the substrate for such vias would have to be in the order of 100 μm, which is extremely thin and not practical for processing on both sides. Handling of such thin wafers requires carrier solutions, i.e. the wafer must be temporarily bonded to a thicker wafer to render it stable enough to be processed as desired.
Furthermore, in modern electronic devices such as mobile phones, the different thermal expansion coefficients for the various materials in the housing, the circuit boards, and the micro chips (MEMS, CMOS and the like), respectively, inevitably will cause problems unless relevant design measures are taken.
Thus, it is not suitable to provide routing by vias directly from each I/O point on a IC chip through the substrate on which the chip is mounted. Instead one provides for the above mentioned redistribution structures on the surface of the substrate on which the chip is mounted. The routings are “fanned out”, i.e. the individual conductive strips diverge from the I/O points to a more widely spaced structure, where vias for routing through the substrate are provided for connectivity to the back-side of the interposer.
However, even with such precautions there will be a tendency for thermal stress in the interface between the I/O points and the substrate. To alleviate this effect a conventional procedure is to provide so called “underfill” in the very small space between the substrate and IC chip, using capillary forces. However, this requires that the vias are completely filled to be hermetically sealed such that there will be no leakage of underfill between the stacked structures, which could lead to improper underfill, degradation of the final product, reliability issues and packing issues, rendering final product useless.
Thus, it is desirable to provide filled vias. However, filling conventional vias with metal again will bring the thermal expansion effects into play, in particular if they were to be provided directly beneath the IC chip.
Also, as mentioned above, from a processing point of view, the thickness of the substrate normally cannot be as small as 100 μm without the use of carriers, but rather 300 μm and more is more reasonable not requiring carriers. However, for 300 μm thick wafers it is difficult not to say impossible to make void free hermetically tight vias of the size desirable, e.g. 15-100 μm in diameter, that extend through the substrate, in a cost efficient manner, i.e. in volume production.
In FIG. 3 there is shown a prior art structure disclosed in applicants own WO 2007/089206 A1. Here, routing 125 from a via to a contact pad 123 on a remote location on the substrate 120 is provided by a two-step etching process, wherein via holes 124 are first made, and then recesses 125 are made in a subsequent step. These routing structures will be in-plane and the vias are filled 126. Thermal expansion issues may occur if high density TSVs of this design are to be used.
In FIG. 4 another prior art via structure is shown, details of which are disclosed in applicants own WO 2010/059118. This via structure comprises a wide and deep part 401 extending form one side BS of the wafer 400, and a shallow and narrow part 402 extending from the other side FS (open vias). When the via is metallized 404, only the walls 406 of the wide part is covered (referred to as a “liner via”) whereas the narrow part 402 is completely filled. This structure is advantageous in that thermal effects due to different expansion properties of metal and silicon will not have a major influence despite close-packing of the vias. It also requires less process time with regards to Electrochemical deposition (ECD) of metal (e.g. Cu) than prior art “bottom-up” plated blind TSVs.
When routing layers are provide on a structure as the one above, a disadvantage is that it results in topography causing passivation issues and more difficult post-processing with second RDL and/or micro-bump fabrication.
In EP-2 165 362 (ÅAC Microtec AB) a process referred to as the XiVia™ process is disclosed. In this process KOH etching is used and when it is scaled to higher densities (i.e. smaller holes with larger aspect ratios) there will be problems with uniformity and removal of the seed layer used in ECD plating step.